1. Field of the Invention
This invention relates to semiconductor fabrication, and particularly to fabricating CMOS transistor devices with an air gap between the N-type and P-type doped regions of a gate electrode for reducing threshold voltage variations that can be caused by dopant cross-diffusion.
2. Description of Background
Integrated circuits often employ active devices known as transistors such as field effect transistors (FETs). A metal-on-semiconductor field effect transistor (MOSFET) includes a silicon-based substrate comprising a pair of impurity regions, i.e., source and drain junctions, spaced apart by a channel region. A gate electrode is dielectrically spaced above the channel region of the silicon-based substrate. The junctions can comprise dopants which are opposite in type to the dopants residing within the channel region. MOSFETs comprising n-type doped junctions are referred to as NFETs, and MOSFETs comprising p-type doped junctions are referred to as PFETs. The gate electrode can comprise a doped semiconductive material such as polycrystalline silicon (polysilicon). The gate electrode can serve as a mask for the channel region during the implantation of dopants into the adjacent source and drain junctions. An interlevel dielectric can be disposed across the transistors of an integrated circuit to isolate the gate areas and the junctions. Ohmic contacts can be formed through the interlevel dielectric down to the gate areas and/or junctions to couple them to overlying interconnect lines.
Integrated circuits comprising pairs of NFET and PFET devices are known as complementary metal-oxide-semiconductor (CMOS) circuits. The NFETs and PFETs of a CMOS circuit can be fabricated from a common gate electrode layer by doping a section of the gate electrode belonging to the NFET with n-type dopants and the section of the gate electrode belonging to the PFET with p-type dopants, followed by annealing the dopants for activation. An undoped section is usually located between the NFET and PFET sections of the gate electrode. Demands for increased performance, functionality, and manufacturing economy for integrated circuits have resulted in extreme integration density and scaling of NFETs and PFETs to very small sizes. The spacing distances between adjacent NFET and PFET devices have been scaled accordingly.
Unfortunately, reducing the spacing between NFET and PFET devices sharing a common gate electrode can lead to dopant cross-diffusion between the NFET and PFET sections of the gate electrode. This cross-diffusion can undesirably cause a shift in the work function of one or both of the NFET and PFET devices, resulting in threshold voltage (VT) variations and thus VT mismatch between those devices. This problem has been observed in 65 nanometer (nm) technology, particularly in static random access memory (SRAM) technology, which includes FETs having Vmin and stability values that are very sensitive to VT mismatch. Severe dopant cross-diffusion is expected in 32 nm technology, which has transistor spacing distances equal to about half of the dopant diffusion length.